Sophie’s Compendium of Things That Talk

From Current Loops to PCI Express

A taxonomy, history and practical review of buses, interfaces, networks and the increasingly elaborate business of moving bits between things.

Part of Sophie’s Cabinet of Computing Curiosities.

Preface: what counts as “talking”?

A connector is a shape. An electrical interface is a set of voltage, current, impedance and timing rules. A link or bus decides how participants share the medium. A protocol defines messages, transactions and error handling. The application decides what those messages mean. They are related, but they are not interchangeable concepts, despite decades of product brochures working very hard to make them so.

Five different layers that marketing departments routinely compress into “port”.

THE FIRST RULE Connector ≠ electrical interface ≠ signalling standard ≠ protocol ≠ bus. USB-C receptacles may expose several radically different capabilities while looking exactly like the one next to it.

This compendium classifies interfaces by physical signalling, topology, arbitration, synchronisation, direction, addressing and the software or firmware needed to make the hardware useful. Rates are given as representative headline figures rather than fake precision. “480 Mbit/s”, “6 Gbit/s”, “128 GT/s” and “800 Gbit/s” are not directly comparable payload numbers; encoding, lanes, duplex, framing and protocol overhead matter.

The document also includes a few interfaces whose main purpose is test, control or memory rather than conventional peripheral I/O. They belong because they reveal the same recurring engineering choices: who may speak, how everyone else knows, what happens when two devices speak together, and which resistor someone forgot to fit at the far end.

Contents

A taxonomy of interfaces and buses

There are several useful axes of classification. None is sufficient alone. A system can be serial electrically but parallel logically; point-to-point physically but part of a switched fabric; full-duplex on the wire but effectively half-duplex at a higher protocol layer. The more modern the interface, the more likely it is to contain several older ideas wearing hats packet headers.

Question	Typical answers	Why it matters
How many conductors carry data?	Parallel, serial, lane-based	Pin count, skew, routing and connector size.
Who can speak?	Fixed controller, master/target, peer-to-peer, token, arbitration	Determines latency, complexity and failure modes.
How is time known?	Separate clock, embedded clock, asynchronous timing	Controls distance, speed and receiver complexity.
How is the medium shared?	Point-to-point, multi-drop, bus, ring, star, switched fabric	Defines contention, termination and isolation.
How is a device selected?	Dedicated chip-select, address, ID, enumeration, discovery	Decides how much configuration pain reaches the user.
What happens on error?	Nothing, parity, CRC, retry, link recovery	Separates “fast on paper” from “survives a real cable”.

Serial, parallel, synchronous and asynchronous

Parallel transfers several bits at once across multiple conductors. Serial moves bits or symbols in sequence, often over one differential pair per direction or per lane. Synchronous links share or recover a clock; asynchronous links agree timing by convention and frame data with start/stop information or other delimiters. These labels describe different things: RS-232 is serial and commonly asynchronous; SPI is serial and synchronous; classic PCI is parallel and synchronous; PCI Express is serial, lane-based and recovers timing from the signalling stream.

Single-ended versus differential

Single-ended signalling measures a conductor against a common reference. Differential signalling measures the difference between a pair. Differential systems generally tolerate common-mode noise and high rates better, which is why modern high-speed buses contain an impressive quantity of carefully routed pairs. The price is that “two wires” does not mean “simple”; impedance, return paths, equalisation and common-mode behaviour still exist, waiting patiently for the layout engineer.

TERMINATION LESSON At sufficiently high edge rates, a wire stops behaving like an abstract connection and starts behaving like a transmission line. Terminators are not decorative punctuation. Their job is to make the impedance discontinuity at the end less exciting.

Current loops, UARTs and the serial ancestry

Current loop: robust, slow and extremely difficult to impress

Teleprinters and early terminals often used current-loop signalling, commonly associated with 20 mA systems. Information was represented by current flowing or not flowing rather than by a precise voltage against a shared ground. The approach tolerated long cable runs and electrically unfriendly environments surprisingly well. It also established an enduring principle: a physically robust interface can outlive a nominally faster one if it works reliably in the place where people actually need it.

The UART: turning parallel bytes into serial patience

A UART converts parallel character data into an asynchronous serial stream and back again. Start bit, data bits, optional parity and stop bit(s) made it possible for two machines to communicate without sharing a continuous clock. The format is ancient by semiconductor standards and remains everywhere: microcontroller consoles, boot loaders, debug headers and equipment that will still be talking long after the web dashboard has stopped receiving security updates.

RS-232, RS-423, RS-422 and RS-485

RS-232 became the familiar single-ended terminal interface: wonderfully interoperable in principle, followed immediately by decades of DTE/DCE confusion, null-modem cables and arguments about whether a particular device really needed RTS/CTS. I’m still working through that lot with a counsellor. RS-423 improved single-ended performance; RS-422 used differential signalling for point-to-point or limited multi-drop operation; RS-485 allowed balanced multipoint buses with multiple transmitters, making it a favourite of industrial control, building systems and equipment that prefers screw terminals to fashion.

Family	Electrical idea	Topology	Character
RS-232	Single-ended voltage signalling	Point-to-point	Simple concept; connector and handshaking folklore vast.
RS-423	Single-ended, improved driver/receiver characteristics	Point-to-point / limited multi-drop	Common on some British micros, less culturally dominant.
RS-422	Balanced differential	Point-to-point / multi-drop receivers	Good distance and noise immunity.
RS-485	Balanced differential, tri-state drivers	Multipoint bus	Industrial survivor; termination and biasing matter.

HISTORICAL NUGGET The word “serial” describes the data path, not the plug. DB-25, DE-9, mini-DINs, modular jacks, headers and bare screw terminals have all carried serial links. This is why collecting cables eventually becomes taxonomy rather than tidying.

Parallel ports, GPIB and the era of many wires

Centronics and IEEE 1284

The classic printer interface took the straightforward route: put a byte on several wires, use handshake lines to say when it is valid, and let the printer admit when it is busy. “Centronics” became a generic name for the ecosystem; IEEE 1284 later standardised bidirectional modes while retaining compatibility with the familiar PC parallel-port hardware. It worked because the distances were short and the job description was modest. It became less attractive as computers got smaller and serial links got cleverer.

IEEE-488 / GPIB: a bus designed for instruments, therefore full of instruments

Hewlett-Packard’s HP-IB evolved into IEEE-488/GPIB, a shared parallel instrument bus with talkers, listeners and a controller. It became laboratory furniture: oscilloscopes, spectrum analysers, power supplies and measurement systems could be chained together with chunky stackable connectors. Its physical bulk is considerable, but so is its persistence. A laboratory full of expensive instruments is a powerful argument against replacing an interface merely because a newer one has a smaller plug.

Why parallel stopped scaling gracefully

Every extra conductor is another signal that must arrive within the sampling window. As rates rise, propagation delay, crosstalk and path-length mismatch become first-order design constraints. Parallel buses can be extremely fast over controlled short distances, but extending them through connectors and cables becomes progressively less amusing. High-speed serial links replace wire-count with encoding, clock recovery and analogue equalisation. The complexity does not disappear; it migrates into silicon where it is easier to manufacture repeatedly.

British microcomputer ingenuity: BBC, Econet, Tube and Sinclair QLAN

The BBC Micro: almost everything is a port

The BBC Micro was designed to be expanded rather than merely admired. The 1 MHz bus, Tube, User Port, printer, disc interface, analogue input, serial interface and optional Econet made the underside and rear of the machine look like an argument against minimalism. Acorn’s 1 MHz bus exposed buffered A0–A7 and D0–D7 plus control signals; FRED and JIM were the memorable names for two page-select regions. The official hardware guidance even discussed termination, buffering, daisy chaining and the way loading altered timing.

SAFETY: MEMORY VERSUS MANUALS  The BBC’s expansion connectors really were accessible from underneath, and the auxiliary low-voltage power connector was mounted on the PSU case. But the original BBC specification explicitly required that there be no exposed mains terminals inside the case, and the service manual treated the PSU as a safety-critical exchange module. So the stronger tale that the 1 MHz bus itself exposed mains to fingers is not supported by the documentation. The machine was adventurous enough without giving the bus 240 V.

The Tube: second processors before “heterogeneous compute” sounded expensive

6502, Z80, 32016 and ARM second-processor lineages all exploited the idea. Conceptually it resembles a modern accelerator relationship more than a conventional dumb peripheral: a narrow, well-defined interface separates two independently capable machines.

Econet: clocked networking for schools

Econet used differential data and clock pairs plus ground, with termination and a network clock forming part of the installation. It was especially suited to the educational environment around the BBC Micro: shared file servers, printers and classroom management without requiring every machine to contain a full contemporary networking stack. The separate clock is a very 1980s answer to a problem modern Ethernet solves differently, but the architectural lesson is timeless: centralise just enough complexity to make cheap endpoints useful.

Sinclair QLAN: two wires, automatic termination and very little ceremony

The QL inherited the network idea from the ZX Spectrum Interface 1. Sinclair’s own manual describes a network of up to 64 stations and recommends ordinary twin-core low-capacitance cable, with a practical hardware limit around 100 metres. The QL service manual reveals the charming part: the two NET jack sockets include 330 Ω termination resistors that are disconnected when plugs are inserted. In a correctly wired chain, only the two end stations retain their resistors, producing a combined pull-down of about 165 Ω. The mechanical act of plugging the cable in therefore helps configure the electrical termination.

The networking software was correspondingly compact. Blocks were acknowledged and retransmitted when necessary; station 0 could be used for broadcast. This is a useful antidote to the idea that useful networking requires a multi-million-line software stack. It requires only that the requirements be modest, the assumptions understood and nobody tries to stream 8K video over bell wire.

The QL ROM-port write anomaly: when READ means WRITE

The original Sinclair QL expansion bus was not inherently deficient. Its main side connector exposed the D0-D7 data bus, A0-A19 address lines and RDWL read/write signal, together with strobes, interrupts and other signals expected of a reasonably comprehensive 68008 expansion interface.

The problem emerged from what people actually did with their QLs. Expansion memory, disk interfaces and particularly the Miracle Systems ecosystem consumed much of the useful expansion capability and address space. By 1989 Miracle was developing its QHD, or QL Hard Disk, while also trying to maintain compatibility with its popular Trump Card (no, a different Trump). Miracle engineer Mike Tomlinson later explained that the Trump Card already occupied almost all the convenient QL address space, leaving the nominally read-only ROM port as the practical place from which to hang the hard-disk interface.

That presented a rather obvious difficulty: a ROM port is designed to read things, not write to them.

Miracle’s solution was gloriously inventive. Reading from the hard disk was straightforward. To send a byte to the controller, however, the software placed that byte onto address lines A8-A1 and performed a word-sized read cycle. The peripheral hardware ignored the philosophical absurdity of the CPU apparently reading something and instead latched those address bits as the byte being written. Higher address lines A9-A13 supplied register selection and read/write control. The word-sized access conveniently gave the controller enough time to capture the value.

Thus, on a sufficiently expanded QL: “to write data, you performed a read from an address containing the data you wanted to write.”

Miracle went further to avoid monopolising even the ROM port. The QHD contained its own EPROM, which appeared during reset so that its device driver could initialise. The QHD then paged its own ROM out, and deliberately caused the QL to inspect the ROM port again, allowing another cartridge – such as SuperToolkit II, a compiler ROM or other peripheral – to remain usable behind it.

That degree of compatibility-minded courtesy deserves a respectful tip of the fascinator from one engineer to another.

This was not merely an amusing laboratory exercise. Tomlinson reported that the resulting QHD was more than seven times faster than Trump Card floppy storage when loading 32 KB using LBYTES, while the contemporary mechanism provided around 40 MB of hard-disk capacity. [40]

Engineering lesson: specifications describe the machine that left the factory; peripheral designers have to support the machine that users have subsequently built. A perfectly adequate expansion bus can become unavailable in practice, and compatibility pressure can produce wonderfully perverse solutions. On the QL, that eventually included making READ mean WRITE.

There are hacks, and then there are hacks elegant enough to deserve preservation.

MYTH-CHECKING LESSON The remembered story was almost right, but attached to the wrong connector. The oddity arose after popular expansions had occupied much of the useful expansion route and address space. So the folklore that “the QL used address lines as data” was basically true. The missing detail was why: not because Sinclair forgot to provide a data bus, but because clever peripheral designers had run out of convenient ways to use it. Lesson: old technical recollections are often worth investigating rather than dismissing. Sometimes the apparently ridiculous bit is true; only the surrounding explanation has suffered a few decades of bit rot.

Other home-micro ways of refusing to agree

Atari SIO made peripherals intelligent and daisy-chainable. Commodore’s IEC serial bus economised on pins and reused concepts from IEEE-488 at a much lower-cost scale. Apple Desktop Bus let keyboards and pointing devices share a simple low-speed link. LocalTalk used inexpensive cabling and a disciplined software stack. The period is a reminder that there was no inevitable path to USB: each vendor optimised around cost, available silicon, software expertise and the accessories it expected users to buy.

Expansion buses: from raw processor pins to packetised lanes

S-100 and the exposed-processor school of architecture

Early microcomputer buses often looked uncomfortably like the CPU itself brought to a connector: address, data, control and power with comparatively little abstraction. S-100 grew from the Altair ecosystem and eventually became IEEE 696. Such buses were flexible because an expansion card could see almost everything. They were also electrically and mechanically unforgiving because an expansion card could see (and potentially reduce to scrap) almost everything.

ISA: jumpers, IRQs and the character-building years

The IBM PC bus evolved into the 8-bit and 16-bit ISA ecosystem. It was open enough to encourage a huge peripheral market, but configuration was often manual: I/O addresses, IRQs and DMA channels could collide, and the operating system could not always rescue you from two cards confidently claiming the same resource. Plug and Play later attempted diplomacy. Anyone who configured a sound card and network adapter on the same machine acquired useful instincts for modern incident response.

PLUG AND PLAY It was said that Plug and Play worked half the time. The PLUG aspect, half of the total, worked all of the time…

MCA, EISA and VLB: three answers to the same discomfort

IBM’s Micro Channel Architecture offered a cleaner, configured, higher-performance design but came with licensing and ecosystem consequences. EISA extended the ISA lineage while remaining more compatible. VESA Local Bus took a more direct route to performance by attaching fast peripherals close to the 486 local bus, producing long connectors and timing limitations that made it gloriously transitional. The market was clearly asking for a bus that was fast, configurable and not tied too intimately to one processor generation.

PCI and PCI-X: configuration becomes civilised

PCI provided a processor-independent shared bus with configuration space and bus mastering. The original mainstream form was 32 bits at 33 MHz; faster and wider variants followed. PCI-X extended the same family for servers, reaching higher clock rates and split transactions. The important shift was cultural as much as electrical: devices could identify themselves and be enumerated rather than requiring a small archaeological dig through jumper tables.

PCI Express: a bus that is really a network wearing a slot

PCI Express kept the PCI software model while replacing the shared parallel electrical bus with point-to-point serial links composed of lanes. Transactions are packetised; switches can create fabrics; link widths can scale from x1 upward. This is one of the central patterns of modern I/O: retain a familiar programming model while quietly replacing the physics underneath it.

Generation	Raw rate per lane	Encoding / signalling note
PCIe 1.x	2.5 GT/s	8b/10b
PCIe 2.x	5 GT/s	8b/10b
PCIe 3.x	8 GT/s	128b/130b
PCIe 4.x	16 GT/s	128b/130b
PCIe 5.x	32 GT/s	128b/130b
PCIe 6.x	64 GT/s	PAM4, FLIT mode, FEC
PCIe 7.0	128 GT/s	PAM4; specification released 2025

CURRENT HORIZON PCI-SIG released PCIe 7.0 Version 1.0 on 11 June 2025. Its raw signalling rate is 128 GT/s per lane, double PCIe 6.x. “GT/s” is deliberately not written as “Gbit/s” because with modern modulation and framing, transfers and useful payload bits are not synonyms.

Storage interfaces: when the disk became a protocol stack

Floppy interfaces: the drive was simpler than the cable made it look

Classic floppy interfaces exposed low-level control: motor select, drive select, direction, step pulses, head selection and raw read/write data. The famous PC ribbon-cable twist helped distinguish drive positions. It was an interface from an era when the controller knew intimate details of the mechanism rather than issuing abstract commands such as “read logical block 12345”.

ST-506/ST-412 and ESDI: controllers still do the thinking

Early hard-disk interfaces such as ST-506/ST-412 carried relatively low-level drive signals to a separate controller. ESDI moved more intelligence toward the drive and raised performance. These systems are useful markers in the long migration of storage intelligence: from controller card, to drive electronics, to a modern SSD containing several processors, flash-translation logic and more firmware than an early workstation.

SASI and SCSI: commands outlive connectors

SCSI’s great achievement was abstraction. Instead of exposing the mechanics of a disk, a host issued commands to logical devices. Parallel SCSI acquired IDs, multiple widths, several electrical variants and a famous appetite for correct termination. The command architecture then escaped its original cabling: T10 notes that SCSI architecture underlies parallel SCSI, SAS, Fibre Channel, iSCSI, USB Attached SCSI and other transports. A protocol family can therefore survive long after its most photogenic connector becomes landfill.

SCSI LESSON  If a chain contains devices with duplicate IDs, missing terminators or termination in the wrong place, the resulting symptoms can impersonate almost any other fault. SCSI taught a generation that “mostly works” is a valid electrical state.

IDE/ATA and ATAPI: move the controller onto the drive

IDE’s conceptual simplification was in its name: Integrated Drive Electronics. The controller functions moved onto the drive and the host interface became ATA. Parallel ATA then accumulated faster modes, 40- and 80-conductor cables, master/slave or cable-select arrangements and ATAPI packet commands for devices such as optical drives. It was vastly easier than many predecessors while retaining enough jumper folklore to prevent complacency.

SATA, SAS and NVMe

Serial ATA replaced the wide PATA ribbon with point-to-point serial links; SATA Revision 3.0 defines 6 Gbit/s signalling. SAS serialised the SCSI enterprise lineage and added dual-port and expander-friendly characteristics. NVMe went further by designing the host software interface around non-volatile memory over PCI Express, with deep parallel queues and low overhead rather than carrying forward assumptions created for rotating disks. As of August 2026 the current NVMe Base Specification is 2.3, released in August 2025, with transports including PCIe, RDMA and TCP.

This progression is worth noticing: the physical storage device becomes less visible to software at exactly the same time that the interface becomes more general. NVMe commands can cross PCIe locally or a network fabric remotely. A disk interface has become an architecture.

Ethernet: from vampire taps to switched fabrics

10BASE5: drill into the cable, what could possibly go wrong?

Thick Ethernet used 50 Ω coaxial cable as a shared bus. Transceivers could attach through “vampire taps” that pierced the cable without cutting it, with AUI cables connecting onward to equipment. The arrangement was clever, physically substantial and hostile to casual rearrangement. It also made the shared-medium nature of Ethernet impossible to ignore: everyone was literally attached to the same electrical conversation.

10BASE2: cheaper coax, identical dependency on continuity

If a station was physically removed along with its T-connector, the two coax tails had to be joined to restore continuity. Failure to do that broke the segment for everybody beyond the new gap. This was an extraordinarily effective way to make one person’s desk move visible across a whole office.

FIELD LORE, NOT A STANDARD There are stories of engineers deliberately biasing (at 240 V AC!) or otherwise abusing the coax shield to make troublesome installations behave differently. Such tricks were not permitted 10BASE2 practice, could create shock/equipment hazards, and are emphatically not instructions, however effectively they discouraged user tampering. The correct fix was boring: continuous 50 Ω coax, proper T-connectors, correct termination and sound bonding. Boring is underrated when several departments are waiting for the network.

CSMA/CD: polite enough until everybody speaks at once

Classic shared Ethernet listened before transmitting and detected collisions while transmitting. A collision was not a moral failure; it was part of the access method. The sending stations exponentially backed off (with a random element to the timing to help avoid repeated collisions) and tried again. This made shared coax and hub-based Ethernet practical without a token or central scheduler, but performance deteriorated as contention grew. Switching eventually isolated collision domains and full-duplex point-to-point links made collision detection irrelevant on modern switched Ethernet.

10BASE-T and the architectural trick of looking like a bus while wiring like a star

Twisted-pair Ethernet changed the physical topology to point-to-point runs between stations and hubs or switches. A hub reproduced the old shared collision domain electrically; a switch learned addresses and forwarded frames selectively. The Ethernet frame and software model survived while the physical network underneath became progressively less like the original coax bus. This is another recurring theme: successful abstractions outlive the physics that created them.

From megabits to hundreds of gigabits

Ethernet expanded through 100 Mbit/s, 1 Gbit/s, 10 Gbit/s and many higher-rate copper and optical families. IEEE 802.3df-2024 standardised 400 and 800 Gbit/s Ethernet. As of August 2026, IEEE P802.3dj has completed its second Standards Association recirculation ballot, which closed on 15 August; 1.6 Tbit/s Ethernet is therefore still in standardisation rather than a finished published standard. Future-tense labels matter; specifications have enough version numbers without time travel.

Networks that nearly won, and several that actually did

Token Ring: permission to speak, circulated politely

Token Ring used a circulating token to grant transmission rights. This made access deterministic in ways attractive to enterprise buyers and removed Ethernet-style collisions. IBM’s implementation often used a Multistation Access Unit, so a network that was logically a ring could be wired in a physical star. It was technically elegant, operationally structured and ultimately defeated in mainstream LANs by Ethernet’s cost, speed and ecosystem momentum. Better engineering does not always win; sometimes the cheaper thing becomes good enough faster.

PRANKSTERS PARADISE Along with the poor naïve apprentices sent to stores for a “Long Stand”, a “Big Weight”, or “Tartan Paint”, some were set the task of searching the machine room floor for an escaped Token from when the Token Ring network was unsafely unplugged.

FDDI: dual rings and serious fibre

FDDI used token passing over fibre, typically with counter-rotating dual rings for resilience. At 100 Mbit/s it was once backbone technology rather than a nostalgic curiosity. Its demise is a useful reminder that “fibre” is not a protocol and does not confer immortality; the optics can remain excellent while the ecosystem moves on.

ARCNET, LocalTalk and the virtue of being adequate

ARCNET achieved a long industrial life with token passing and flexible physical arrangements. Apple LocalTalk provided inexpensive networking using serial hardware and simple cabling; PhoneNet later made ordinary telephone-style wiring practical. These systems were not trying to win a benchmark spreadsheet. They were trying to let real computers share printers and files at a price people could tolerate. That is often how standards acquire cultural persistence.

Fibre Channel: network-shaped storage I/O

Fibre Channel developed into a high-reliability switched fabric for storage and data-centre use. Despite the name, it is not restricted to optical fibre. Its existence is taxonomically useful because it sits at the border between “network” and “storage bus”: SCSI commands can travel over it, yet the fabric has its own addressing, switching and service model. Categories are conveniences, not laws of physics.

External serial convergence: USB, FireWire and Thunderbolt

USB: one host, many devices, eventually nearly everything

USB replaced a remarkable collection of PC peripheral interfaces by combining power, enumeration, device classes and a host-controlled serial bus. Version 1.x gave low/full-speed devices a common home; USB 2.0 raised headline speed to 480 Mbit/s; USB 3.x added SuperSpeed lanes; USB4 adopted a more fabric-like architecture capable of tunnelling other protocols. The engineering success is enormous. The naming history is what happens when success is administered by committees.

USB-C LESSON USB-C is a connector system, not a promise that every cable or port supports the same data rate, video modes or power. The Cable Menagerie already prosecuted this offence. This volume merely records that the confusion exists one layer above the metal as well.

FireWire / IEEE 1394: peer-to-peer before USB learned new tricks

IEEE 1394 was a high-speed serial bus designed for external peripherals, with peer-to-peer behaviour, bus mastering and isochronous transfer attractive to digital video and audio. Devices could be daisy-chained without requiring every transaction to be orchestrated by a conventional PC host. It was technically sophisticated and, for some workloads, beautifully suited. USB’s price and ubiquity eventually dominated general peripherals, while FireWire’s direct-memory-access capabilities also became an instructive security problem.

Thunderbolt: PCI Express escapes the case

Thunderbolt combines high-speed data, display and PCIe tunnelling over an external cable. Modern generations share the USB-C connector, which is convenient physically and an educational opportunity conceptually. Thunderbolt 5 provides 80 Gbit/s bidirectional bandwidth and can use Bandwidth Boost to provide up to 120 Gbit/s in the display-heavy direction while retaining 40 Gbit/s the other way. Intel describes it as built on USB4 v2, DisplayPort 2.1 and PCIe Gen 4.

USB4 Version 2.0

The USB-IF published the current USB4 Version 2.0 specification package in April 2026. The architecture supports the 80 Gbit/s class over USB-C cabling and reinforces the larger trend: a modern “peripheral bus” is increasingly a managed fabric capable of carrying several kinds of traffic rather than a single simple byte stream.

Board-level and embedded buses: I²C, SPI, CAN and friends

I²C: two signal wires and a great deal of etiquette

Philips, now NXP, developed I²C as a two-wire inter-IC control bus: SDA for serial data and SCL for the serial clock. Devices use open-drain/open-collector style signalling with pull-ups, allowing wired arbitration and shared lines. Addressing, acknowledgements, repeated starts and optional clock stretching make it far more structured than “two wires” suggests. NXP’s current user manual describes modes from 100 kbit/s Standard-mode through multi-megabit variants.

SPI: fast, simple and deliberately underspecified

SPI commonly uses clock, controller-out/peripheral-in, peripheral-out/controller-in and one or more chip-select lines. It is synchronous and efficient, but there is no single universal higher-level framing or addressing convention. Two “SPI devices” may disagree about clock polarity, phase, word length and transaction semantics while both being perfectly entitled to the label. Simplicity at one layer merely exports decisions upward.

1-Wire: one data conductor, because two was apparently extravagant

Dallas Semiconductor’s 1-Wire family carries communication, and in some arrangements parasitic power, over a single data conductor plus ground. Unique device identifiers make multi-drop networks practical. It is slower than I²C or SPI but excels where wiring cost and identity matter more than throughput: sensors, identification devices and small distributed systems.

CAN: arbitration without the shouting match

Controller Area Network uses dominant and recessive bus states so contenders can arbitrate while transmitting. A sender that transmits recessive but observes dominant knows a higher-priority identifier is winning and stops without corrupting the winning frame. This non-destructive arbitration is an elegant answer to shared-medium access. Bosch notes that Classical CAN is limited to 1 Mbit/s and 8 data bytes per frame; CAN FD, introduced in 2012, expands payloads to 64 bytes and permits a faster data phase. CAN XL extends the family further toward Ethernet-class payloads and rates.

LIN and the hierarchy of automotive networks

Local Interconnect Network provides a lower-cost single-master serial link for less demanding automotive functions. It commonly coexists with CAN rather than replacing it. This is another important lesson: systems do not converge on one perfect bus. They stratify. Expensive high-performance links go where they are needed; cheap simple links survive everywhere else.

JTAG: test interface, debug interface, security problem

IEEE 1149.1 JTAG began as a boundary-scan test architecture but became a powerful route into device debug and programming. That makes it invaluable on a bench and potentially hazardous in a deployed product. An unprotected debug path can turn physical access into privileged control. Interfaces designed for manufacturing have an unfortunate habit of remaining extremely useful after manufacturing ends.

Specialist survivors: MIDI, DMX and control links

MIDI: 31.25 kbaud and still culturally immortal

MIDI 1.0 was published in 1983. The original electrical interface uses an asynchronous 31.25 kbaud stream and 5-pin DIN connections with galvanic isolation at the receiver to avoid audio ground-loop problems. By modern bandwidth standards this is geological. By interoperability standards it is magnificent: decades of instruments can still exchange notes, controllers and timing because the problem domain did not require anyone to multiply the data rate by a thousand every three years.

DMX512: lighting prefers deterministic simplicity

DMX512 uses an RS-485-family differential physical layer to carry control slots for stage lighting and effects. It is a strong example of layering: the underlying electrical standard is generic, while the application protocol is specialised. The same broad electrical idea can control a theatre dimmer, an industrial sensor network or something entirely unrelated because electrical signalling does not dictate meaning.

SURVIVAL LESSON Standards live longest when they solve a bounded problem, are cheap to implement, and do not require both ends to be replaced together. MIDI’s modest rate is not a flaw if a note-on message still arrives before the musician notices.

Why serial beat parallel

At low speeds, sending eight, sixteen or thirty-two bits simultaneously looks obviously faster than sending them one after another. At high speeds, “simultaneously” becomes expensive. Each trace or cable conductor has propagation delay, loss, coupling and a receiver threshold. Keeping a wide group inside one timing window across connectors and cable becomes progressively difficult.

High-speed serial links narrow the physical channel and compensate with much faster signalling, embedded clocks, scramblers, encoding, equalisation, training, forward-error correction and multiple independent lanes. Modern PCI Express and Ethernet PHYs are therefore partly digital protocols and partly very accomplished analogue communications systems.

Baud, bit/s and transfers/s: three units walking into the same datasheet

Baud is symbol rate. Bit/s is information-bit rate at a defined layer. Transfers per second can mean something different again. NRZ conveniently maps one binary symbol to one bit before encoding overhead is considered; PAM4 carries two bits of symbol information by using four amplitude levels, which is why PCIe 6.0 and 7.0 can double the bit information rate without doubling the fundamental symbol rate in the same way. Treat any headline number without its layer and encoding as an invitation to read the footnotes carefully.

Encoding overhead is not wasted if it buys the link

8b/10b sacrifices raw efficiency for transition density, DC balance and control characters. 64b/66b and 128b/130b reduce overhead. FLIT modes, CRCs and forward-error correction add structure again at extreme rates because recovering from occasional symbol errors is cheaper than pretending the channel is perfect. “Overhead” is what a protocol engineer calls the information that makes the useful information arrive intact.

Security: a bus is a trust boundary

DMA: performance feature, privilege-escalation opportunity

Bus mastering lets devices transfer data without forcing the CPU to copy every byte. That is essential for performance and dangerous when a physically accessible or compromised device can reach arbitrary memory. FireWire and Thunderbolt made the issue particularly visible because high-performance peripheral buses escaped the chassis. Modern IOMMUs and operating-system DMA protections exist partly to put memory-access boundaries back around devices that the electrical architecture otherwise trusts.

Hot plug changes the threat model

A soldered-down peripheral is an engineering assumption. A hot-pluggable external port is a user-controlled trust boundary. USB devices can identify as keyboards, network adapters, storage or composite devices; Thunderbolt can tunnel PCIe; debug ports may expose privileged processor control. Interface security therefore includes enumeration policy, device identity, firmware trust, DMA isolation and deciding whether the port should be accessible at all.

Shared buses leak information and influence

Multidrop buses may expose traffic to every attached participant electrically even when only one address is intended to respond. Malicious or faulty devices can hold lines, disrupt arbitration, spoof identities or force error recovery. Industrial networks often assume physical trust because they were designed before every cable became a potential cyber boundary. Retrofitting authentication is harder than adding a checksum.

SilentGlass: when even the monitor is untrusted

A display cable feels intuitively one-way: the computer produces pixels and the monitor displays them. Modern HDMI and DisplayPort connections are considerably less innocent. Alongside the main audio/video stream sit control, discovery, capability-negotiation and management exchanges. The computer therefore accepts and processes information originating from the device at the other end of a cable which users routinely plug into meeting-room screens, hotel televisions, docking stations and assorted smart displays of uncertain ancestry, provenance, and potential hostility. Remember, your display device may be running more than some basic firmware – there may be an entire Android (that is, Linux) system available in there for customisation and/or subversion.

In 2026 the UK National Cyber Security Centre (NCSC) made this problem unusually tangible with SilentGlass, a hardware device developed originally within NCSC and subsequently licensed to Goldilock Labs, working with Sony UK Technology Centre for manufacture. SilentGlass sits inline between a computer and its HDMI or DisplayPort display connection and is intended to block unexpected or malicious behaviour crossing that interface. NCSC says the technology had already been deployed on Government estates and approved for use in high-threat environments before its wider commercial release. [39]

The interesting lesson is larger than the product itself. SilentGlass treats the physical interface as an enforceable security boundary, rather than assuming that anything connected to a familiar socket deserves to converse freely with the software stack behind it. That is a useful corrective to decades of peripheral design in which convenience steadily accumulated negotiation protocols, sideband channels and increasingly intelligent devices behind connectors that still look reassuringly passive.

A monitor, in other words, is no longer necessarily just something you talk to. It may talk back. And it may snarl and hiss, and it may do so in a dialect your GPU driver is nevertheless expected to understand, and must protect itself against.

SECURITY LESSON Connector direction is not trust direction. A cable whose principal purpose is to carry output may still provide inbound control paths into complex firmware, drivers and operating-system code. Assess the complete interface, not the arrow on the block diagram. ASSESSOR’S RULE When reviewing an interface, ask two separate questions: “Can this device communicate?” and “What authority does communication grant it?” A bus that can perform DMA, reset a processor, reflash firmware or inject input events is not merely a data path.

Failure modes and the dark art of making links work

Symptom	Likely layer	Classic causes
Nothing responds	Power / physical / addressing	Wrong cable, missing ground, dead terminator, wrong address, disabled port.
Works only with one device	Loading / arbitration	Too much capacitance, duplicate IDs, stubs, pull-ups or bias wrong.
Works when cable is short	Signal integrity	Loss, reflections, skew, poor termination, wrong cable impedance.
Works until another card is fitted	Resources / power / timing	IRQ/DMA conflict, bus loading, PSU margin, enumeration ordering.
Fast mode fails, slow mode works	PHY / timing	Channel loss, equalisation, rise time, crosstalk, clock margin.
Intermittent corruption	Integrity / grounding	Connector wear, EMI, ground shift, marginal termination, bad shielding.
System compromised by peripheral	Security architecture	DMA, debug access, spoofed device class, untrusted firmware.

Termination and stubs

A shared transmission line should look electrically like the impedance it expects to see at its ends. Extra stubs create reflections; excessive stub length becomes increasingly damaging as edge rates rise. 10BASE2 made this visible with literal 50 Ω terminators. Modern high-speed serial links hide much of the termination inside PHYs, but transmission-line physics has not been repealed.

Grounds, shields and the temptation to treat them as spare wires

Shields control electromagnetic behaviour and provide defined return or bonding functions according to the interface design. They are not a free conductor for improvised signalling or power. Deliberately putting unexpected potentials on a shield may appear to “fix” a particular fault while creating shock, equipment-damage, EMC and common-mode problems elsewhere. A workaround that makes the fault disappear is not necessarily a repair; sometimes it is merely relocating the evidence.

Hot plugging: designed feature or expensive experiment?

Modern interfaces define connector sequencing, pre-charge contacts, power limits and state machines for hot insertion. Many older buses do not. Pulling an ISA card, SCSI device or unprotected ribbon connector while powered is not a diagnostic technique; it is a way to discover which component reacts fastest to uncontrolled transients. “It survived last time” is not a standard.

Checksums, CRCs and retries

As links became faster and channels less forgiving, error detection moved from optional nicety to architectural necessity. Parity can detect simple errors; CRCs cover frames or packets; modern high-speed links may combine CRC with replay or forward-error correction. A fast link that occasionally corrupts data undetected is not high performance. It is a corruption generator with excellent benchmark numbers.

The future: coherent fabrics, chiplets and terabit links

PCIe 7.0: 128 GT/s and the analogue reality of digital logic

PCIe 7.0 doubles the previous generation to 128 GT/s per lane while retaining the PCI Express architectural lineage. At these rates board material, connector loss, retimers, equalisation and layout are not implementation trivia; they are part of whether the specification can exist outside a simulator. The “digital bus” has become a communications channel necessarily engineered with RF-like care.

CXL 4.0: memory joins the fabric

Compute Express Link builds coherent and memory-oriented protocols on PCIe physical infrastructure. CXL 4.0, released in November 2025, doubles maximum data rate to 128 GT/s and adds features including bundled ports and enhanced memory reliability/availability/serviceability. The important conceptual change is that expansion is no longer only about I/O devices: accelerators and memory can participate in a coherent system fabric.

UCIe 3.0: the bus moves inside the package

Universal Chiplet Interconnect Express standardises die-to-die links so complex processors can be assembled from interoperable chiplets rather than one monolithic die. UCIe 3.0, released in August 2025, supports 48 and 64 GT/s data rates. This is the same historical pattern at a new scale: standardise the boundary, then let specialists innovate on either side of it.

Ethernet beyond 800G

IEEE 802.3df-2024 makes 800 Gbit/s Ethernet a standardised reality. The P802.3dj project is extending the family to include 1.6 Tbit/s operation; as of August 2026, IEEE P802.3dj has completed its second Standards Association recirculation ballot, which closed on 15 August; 1.6 Tbit/s Ethernet is therefore still in standardisation rather than a finished published standard. The fact that Ethernet can plausibly span a 1980s coax segment and a terabit optical link without becoming a completely different software concept is one of the great successes of layered engineering.

What probably does not change

Future interconnects will use faster signalling, more optical links, smarter retimers, coherent memory semantics and increasingly elaborate negotiation. They will still fail because of bad connectors, incorrect assumptions, marginal channels, firmware, interoperability and someone plugging the right-shaped thing into a port that does something else. Progress is real. So is continuity.

Do not expect to hear anyone say “this link is too fast”.

Master taxonomy and comparison tables

The table deliberately mixes internal buses, peripheral links, LAN technologies and embedded interfaces. That is the point: they are all solutions to the same family of problems at different scales. Rates are representative headline rates or common historical values, not promises of application throughput.

Family	Era	Physical/logical form	Representative rate	Primary use	2026 status / lesson
20 mA current loop	Teleprinter era–	Serial, point-to-point/loop	~110 b/s to kb/s	Terminals / teleprinters	Legacy / industrial niches
UART async serial	1970s–	Serial point-to-point	Device-defined	Console / embedded	Universal building block
RS-232	1960s–	Single-ended serial	Typically kb/s; higher in practice	Terminal / modem	Survivor / legacy
RS-423	1970s–	Single-ended serial	Higher than classic RS-232	Serial peripherals	Legacy
RS-422	1970s–	Differential serial	Up to multi-Mbit/s by implementation	Industrial / long reach	Survivor
RS-485	1980s–	Differential multipoint	Up to multi-Mbit/s by distance	Industrial control	Major survivor
Centronics	1970s–	Parallel point-to-point	Handshake-limited	Printers	Legacy
IEEE 1284	1990s–	Bidirectional parallel	Mode-dependent	PC peripherals	Legacy
IEEE-488 / GPIB	1970s–	Parallel shared bus	~1 MB/s class historically	Instrumentation	Specialist survivor
BBC 1 MHz bus	1981–	8-bit parallel expansion	1 MHz bus cycles	BBC peripherals	Retro
Acorn Tube	1981–	Register-based host/second CPU link	Architecture-specific	Second processors	Historically important
Econet	1980s–	Clocked multidrop network	100s kbit/s class by generation	Schools / Acorn LAN	Retro
Sinclair QLAN	1983–	2-wire multidrop	Low-speed proprietary	QL / Interface 1 LAN	Retro curiosity
Atari SIO	1979–	Serial daisy-chain	Proprietary	Home-computer peripherals	Retro
Commodore IEC	1980s–	Serial multidrop	Low-speed proprietary	Drives / printers	Retro
Apple ADB	1986–	Single-wire data bus	10 kbit/s class	Keyboard / mouse	Legacy
S-100 / IEEE 696	1975–	Parallel backplane	CPU-era dependent	Microcomputer expansion	Historic
ISA 8-bit	1981–	Parallel shared bus	4.77/8 MHz era	PC expansion	Historic
ISA 16-bit	1984–	Parallel shared bus	8 MHz class	PC expansion	Legacy
MCA	1987–	Parallel configured bus	10 MHz class	IBM PS/2 expansion	Extinct
EISA	1988–	32-bit parallel	8.33 MHz	Server / PC expansion	Extinct
VESA Local Bus	1992–	32-bit local parallel	CPU-clock linked	486 graphics / I/O	Very extinct
PCI	1992–	32/64-bit shared parallel	33/66 MHz	General expansion	Legacy
PCI-X	1998–	64-bit shared parallel	up to 533 MHz family	Servers	Legacy
PCIe 1.x	2003–	Serial point-to-point lanes	2.5 GT/s/lane	General expansion	Legacy
PCIe 3.x	2010–	Serial point-to-point lanes	8 GT/s/lane	General expansion	Still encountered
PCIe 5.x	2019–	Serial point-to-point lanes	32 GT/s/lane	Servers / accelerators	Current
PCIe 6.x	2022–	PAM4 serial lanes	64 GT/s/lane	High-end compute	Current / emerging
PCIe 7.0	2025–	PAM4 serial lanes	128 GT/s/lane	Future high-end compute	Specification current
Floppy interface	1970s–	Parallel/control lines	Controller dependent	Floppy drives	Legacy
ST-506/ST-412	1980s–	Low-level disk interface	~5–10 Mbit/s family	Hard disks	Extinct
ESDI	1980s–	Enhanced disk interface	10–20+ Mbit/s family	Hard disks	Extinct
Parallel ATA / IDE	1986–	16-bit parallel point-to-point-ish	up to 133 MB/s UDMA	Drives	Legacy
ATAPI	1990s–	ATA packet command layer	ATA-dependent	Optical / removable	Legacy
Parallel SCSI	1980s–2000s	Parallel shared bus	5–320 MB/s families	Storage / peripherals	Legacy
SAS	2000s–	Serial point-to-point/fabric	multi-Gbit/s generations	Enterprise storage	Current
SATA	2003–	Serial point-to-point	1.5 / 3 / 6 Gbit/s	Storage	Current / mature
Fibre Channel	1990s–	Serial switched fabric	Many generations	Storage networking	Current
NVMe over PCIe	2010s–	PCIe queues / point-to-point	PCIe-dependent	SSD / accelerators	Current
NVMe over Fabrics	2010s–	RDMA / TCP / FC transports	Network-dependent	Disaggregated storage	Current
10BASE5	1980s–	50 Ω coax shared bus	10 Mbit/s	Ethernet LAN	Historic
10BASE2	1980s–	50 Ω thin coax bus	10 Mbit/s	Ethernet LAN	Legacy / retro
10BASE-T	1990s–	Twisted-pair star	10 Mbit/s	Ethernet LAN	Legacy
100BASE-TX	1990s–	Twisted-pair star	100 Mbit/s	Ethernet LAN	Legacy / embedded
1000BASE-T	1999–	4-pair twisted-pair	1 Gbit/s	Ethernet LAN	Ubiquitous
10GBASE family	2000s–	Copper/fibre point-to-point	10 Gbit/s	LAN / DC	Current
400/800GbE	2020s–	High-speed copper/optical	400/800 Gbit/s	Datacentre / backbone	Current
1.6TbE P802.3dj	2020s–	High-speed optical/electrical	1.6 Tbit/s target	Future Ethernet	In standardisation
Token Ring	1980s–1990s	Logical ring / token	4/16 Mbit/s common	Enterprise LAN	Extinct mainstream
FDDI	1980s–2000s	Dual fibre token ring	100 Mbit/s	Backbone LAN	Legacy
ARCNET	1970s–	Token bus/star	2.5 Mbit/s classic	Industrial / LAN	Niche legacy
LocalTalk	1980s–1990s	Serial network	230.4 kbit/s	Apple LAN	Legacy
USB 1.1	1998–	Host-controlled serial tree	1.5/12 Mbit/s	Peripherals	Legacy
USB 2.0	2000–	Host-controlled serial tree	480 Mbit/s	Peripherals	Ubiquitous
USB 3.2	2010s–	SuperSpeed lanes + USB2	up to 20 Gbit/s	Peripherals/storage	Current
USB4 v2	2020s–	Tunnelling fabric over USB-C	80 Gbit/s class	External high speed	Current spec
IEEE 1394 / FireWire	1990s–	Peer-to-peer serial bus	400/800 Mbit/s common	AV / storage	Legacy
Thunderbolt 3/4	2010s–	PCIe/DP tunnelling	40 Gbit/s	External high speed	Current / mature
Thunderbolt 5	2020s–	USB4v2/PCIe/DP fabric	80 Gbit/s; boost 120	External high speed	Current
I²C	1980s–	2-wire open-drain bus	100 kbit/s to multi-Mbit/s modes	Inter-IC control	Ubiquitous
SPI	1980s–	Clocked serial + chip select	Implementation-defined	Inter-IC high speed	Ubiquitous
1-Wire	1990s–	Single data conductor + ground	Low speed	Sensors / ID	Survivor
CAN Classic	1980s–	Differential arbitration bus	up to 1 Mbit/s	Automotive / industrial	Ubiquitous
CAN FD	2010s–	Differential arbitration bus	Faster data phase; 64-byte payload	Automotive / industrial	Current
CAN XL	2020s–	Next-gen CAN	up to ~20 Mbit/s implementations	Automotive	Emerging
LIN	1990s–	Single-master serial bus	up to 20 kbit/s class	Low-cost automotive	Current
MIDI 1.0 DIN	1983–	Opto-isolated serial current loop	31.25 kbaud	Musical control	Legendary survivor
DMX512	1980s–	RS-485-family differential	250 kbit/s	Stage lighting	Ubiquitous specialist
JTAG / IEEE 1149.1	1990s–	Serial test access port	Clock-defined	Test / debug	Ubiquitous
CXL 4.0	2025–	Coherent protocols on PCIe PHY	up to 128 GT/s	Memory / accelerators	Current spec
UCIe 3.0	2025–	Die-to-die chiplet link	48/64 GT/s	Chiplets	Current spec

Choosing an interface by requirement

Requirement	Usually favours	Watch for
Long distance / noisy environment	Differential serial / fibre	Ground potential, isolation, termination, optical budget.
Cheap embedded control	I²C, SPI, LIN, UART	Address conflicts, pull-ups, chip-select count, debug exposure.
Hard real-time shared control	CAN / deterministic fieldbus	Priority starvation, bus loading, fault confinement.
High-throughput internal I/O	PCIe / CXL	Lane count, thermals, retimers, DMA isolation.
External general peripherals	USB / USB4	Connector ≠ capability; power and cable labelling.
Enterprise storage	SAS / NVMe / FC	Multipathing, queueing, firmware, fabric failure domains.
Legacy recovery	Whatever the device expects	Readers, terminators, adapters, software and patience.

Conclusions: the wire is never just a wire

Interface history begins with wonderfully direct ideas: current means mark, no current means space; put eight bits on eight wires; pass a token; terminate the far end. It then becomes progressively less direct because speed, scale and interoperability demand more machinery. Modern links train themselves, negotiate lanes and power, equalise lossy channels, tunnel other protocols, correct errors and sometimes provide coherent access to memory in another device.

Yet the old engineering lessons remain intact. Shared media need arbitration. Transmission lines need controlled impedance. Devices need identities. Receivers need timing. Fast peripherals need memory protection. And if the cable is the network, unplugging the cable may indeed unplug everybody else.

The future is likely to contain faster serial fabrics, more optics, coherent memory links, chiplet interconnects and network speeds that make early hard disks look like punctuation. It will also contain UART headers, I²C sensors, CAN nodes and MIDI instruments, because technologies survive when they continue solving the problem they were built to solve.

Perhaps that is the useful taxonomy after all: not “old” and “new”, but “abstraction that survived” and “physical implementation we eventually escaped”. Ethernet escaped the coax. SCSI escaped the ribbon cable. PCI escaped the parallel backplane. The successful idea keeps moving even after the connector appears in a museum.

THE LAST RULE When an interface misbehaves, identify the layer before changing the cable. When the cable really is the problem, check the terminators before rewriting the protocol. And never energise a shield merely because the network has annoyed you.

Glossary

• Arbitration: Rules deciding which participant may use a shared medium.
• Baud: Symbols transmitted per second; not necessarily equal to bits per second.
• Bus mastering: Ability of a device to initiate transfers, often including DMA.
• Collision domain: Set of classic shared-Ethernet stations whose simultaneous transmissions can collide.
• CRC: Cyclic redundancy check used to detect transmission errors.
• DMA: Direct memory access: device transfers to/from memory without CPU copying each byte.
• Differential signalling: Information represented by voltage difference between a pair of conductors.
• Enumeration: Process by which a host discovers and configures connected devices.
• FEC: Forward error correction; redundancy that allows some errors to be corrected without retransmission.
• FLIT: Flow-control unit used as a fixed-size transfer structure in modern high-speed interconnects.
• GT/s: Giga-transfers per second; a transfer-rate unit, not automatically equivalent to Gbit/s payload.
• IOMMU: I/O memory-management unit used to control device/DMA access to memory.
• Multidrop: Several devices attached to the same physical signalling medium.
• PAM4: Four-level pulse-amplitude modulation, carrying two bits of symbol information per symbol.
• PHY: Physical-layer circuitry implementing the electrical or optical link.
• Stub: Branch off a transmission line; excessive length can produce reflections.
• Termination: Impedance presented at a transmission-line end to control reflections.
• Topology: Physical or logical arrangement of communicating nodes.
• UART: Universal asynchronous receiver/transmitter.
• Wired-AND / open drain: Shared-line arrangement in which devices actively pull a line one way and release it for the opposite state.

References and further reading

[1] BBC 1981 Microcomputer System Technical Specification (reproduced archive): electrical and mechanical safety requirements. https://www.retroisle.com/general/bbc_literacy_project.php

[2] Wise Owl, A Hardware Guide for the BBC Microcomputer (1983): PSU, 1 MHz bus and expansion guidance. https://ftp.nvg.ntnu.no/pub/bbc/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw_03.htm

[3] Acorn, BBC Microcomputer Service Manual: 1 MHz bus, PSU and safety servicing requirements. https://acorn.huininga.nl/pub/unsorted/manuals/BBC%20Microcomputer%20Service%20Manual-HTML/BBCServiceManual.html

[4] Sinclair Research, QL Service Manual (1985): 68008 buses and peripheral control. https://sinclairql.net/srv/qlsm1.html

[5] Sinclair Research, QL Service Manual: QLAN jack termination circuitry. https://www.oldcomputers.it/parts/sinclair/QL/docs/qlsm/qlsm1_en.html

[6] Sinclair Research, QL Concepts: peripheral expansion connector signals. https://www.sinclairql.net/djw/docs/ebooks/olqlug/QL%20Manual%20-%20Concepts.htm

[7] Sinclair Research, QL Technical Guide (1984). https://sinclairql.speccy.org/archivo/docs/sys/QL_Technical_Guide.pdf

[8] IEEE SA, IEEE 1284-2000: Bidirectional Parallel Peripheral Interface. https://standards.ieee.org/standard/1284-2000.html

[9] IEEE SA, IEEE 1394-2008: High Performance Serial Bus. https://standards.ieee.org/standard/1394-2008.html

[10] Cisco, Ethernet AUI port and 10BASE2/10BASE5/10BASE-T cable specifications. https://www.cisco.com/c/en/us/support/docs/routers/1600-series-routers/46791-ethaui.html

[11] IBM AIX documentation, Ethernet network-interface troubleshooting: 10BASE2 T-connectors and 50 Ω cable. https://www.ibm.com/docs/en/aix/7.2.0?topic=interfaces-tcpip-problems-ethernet-network-interface

[12] IEEE 802.3, P802.3df Task Force: approval of IEEE Std 802.3df-2024 for 400/800 GbE. https://www.ieee802.org/3/df/index.html

[13] IEEE 802.3 ballot announcements: P802.3dj 1.6 Tb/s Ethernet ballot status. https://www.ieee802.org/3/ballots/announce.html

[14] PCI-SIG, PCIe 7.0 Version 1.0 release: 128 GT/s. https://pcisig.com/specifications/pcie-70-specification-version-03-now-available-members

[15] PCI-SIG, PCI-X FAQ: PCI/PCI-X lineage and rates. https://pcisig.com/how-are-pci-x-versions-10-and-20-related-pci-are-they-same

[16] PCI-SIG, PCI Express architecture overview. https://pcisig.com/what-pci-express-pcie-architecture

[17] T10 Technical Committee, Introduction to T10 and SCSI architecture family. https://www.t10.org/intro.htm

[18] T10, SCSI Architecture. https://www.t10.org/scsi-3.htm

[19] SATA-IO, SATA naming guidelines and 6 Gbit/s SATA Revision 3.0. https://sata-io.org/developers/sata-naming-guidelines

[20] SATA-IO, SATA ecosystem technical overview. https://sata-io.org/developers/sata-ecosystem

[21] NVM Express, NVMe Base Specification 2.3. https://nvmexpress.org/specification/nvm-express-base-specification/

[22] NVM Express, NVMe over PCIe Transport Specification. https://nvmexpress.org/specification/nvme-over-pcie-transport-specification/

[23] NVM Express, NVMe over TCP Transport Specification. https://nvmexpress.org/specification/tcp-transport-specification/

[24] USB-IF, USB4 Specification Version 2.0 (April 2026). https://www.usb.org/document-library/usb4r-specification-v20

[25] USB-IF, USB Document Library: USB 2.0 and USB4 specification history. https://www.usb.org/documents

[26] Intel, Thunderbolt 5 connectivity standard. https://newsroom.intel.com/client-computing/intel-introduces-thunderbolt-5-standard

[27] Intel, Thunderbolt technology overview. https://www.intel.com/content/www/us/en/architecture-and-technology/thunderbolt/overview.html

[28] NXP, UM10204 I²C-bus Specification and User Manual Rev. 7.0. https://www.nxp.com/docs/en/user-guide/UM10204.pdf

[29] Bosch, CAN protocols: Classical CAN, CAN FD and CAN XL. https://www.bosch-semiconductors.com/products/ip-modules/can-protocols/

[30] Bosch, CAN XL protocol overview. https://www.bosch-semiconductors.com/products/ip-modules/can-protocols/can-xl/

[31] MIDI Association, MIDI 1.0 specifications. https://midi.org/specs

[32] MIDI Association, MIDI history 1981–1983 and the adoption of 31.25 kbaud. https://midi.org/midi-history-chapter-6-midi-begins-1981-1983

[33] MIDI Association, MIDI 1.0 Electrical Specification update. https://www.midi.org/wp-content/uploads/wpforo/default_attachments/1709416667-ca33-MIDI-10-Electrical-Specification-Update.pdf

[34] CXL Consortium, CXL 4.0 overview. https://computeexpresslink.org/about-cxl/

[35] CXL Consortium, Introducing CXL 4.0. https://computeexpresslink.org/resource/introducing-compute-express-link-cxl-4-0-significant-improvements-in-bandwidth-connectivity-memory-maintenance-and-security/

[36] UCIe Consortium, UCIe 3.0 press release. https://www.uciexpress.org/press-releases

[37] UCIe Consortium, UCIe specifications. https://www.uciexpress.org/specifications

[38] IEEE 802.3, P802.3dj public area. https://www.ieee802.org/3/dj/

[39] National Cyber Security Centre, 22 April 2026.
https://www.ncsc.gov.uk/news/world-first-ncsc-engineered-device-secures-vulnerable-display-links
https://www.gov.uk/government/case-studies/hm-government-licensing-cyber-security-tech-for-a-global-market

[40] Mike Tomlinson, “Code Name QHD”, QUANTA, Volume 7 Issue 1, February 1990, pp. 12–13. The contemporary article explicitly explains the Trump Card address-space problem, writing via A8–A1 during a word-sized read, A9–A13 control, paging the QHD EPROM back out, and the “over seven times faster” figure.
https://qxl.win/quanta/QuantaVol7Iss01Feb1990.pdf

Web sources checked 17 August 2026. Current-standard statements are dated accordingly; historical rates are representative because many interface families contain multiple revisions, modes and physical layers.